TI TIVA TM4C123g learning notes （1)- Exception Model & Interrupts

這兩天為了實作Interrupt，學了一點有關Arm Cortex M4 的Exception實作方法，趕緊來做個筆記！都是從datasheet 第一手資料學習整理得的重點。其中有些圖表有版權問題，我就不貼了～（其實因為還要上傳圖片好麻煩啊～～～）

Exception Model:

Interrupts: asynchronous events triggered by external events(e.g. serial ports, GPIOs, etc.) => So the processor will complete the instruction it’s doing first, then serve the asynchronous interrupt (If the interrupt is a Reset then this is not the case). There are 78 different interrupts.

Exceptions: Interrupts are a subset of Exceptions.

1. Exception Handling:  ARM Cortex-M4F uses NVIC(Nested Vectored Interrupt Controller), which also supports tail-chaining of interrupts.

      2.   Exception States:

• Inactive: not active
• Pending: The exception is waiting for the processor to get serviced.
• Active: Being serviced by the processor but has not completed. 
• Active and Pending: The exception that is being serviced by the processor and there is a pending exception from the same source which is waiting to be serviced.

      3.  Exception Types:

• Reset: (Priority -3) It stops the processor AT ANY POINT of the instruction. When it is de-asserted, processor starts executing the instruction from the address provided by the reset entry in the vector table.
  
• Non Maskable Interrupt(NMI): (Priority -2) Can be asserted by the peripheral or by sw. NMI can not be masked or preempted by the other exceptions other than Reset.

• HardFault: (Priority -1) Error during processing the exceptions or when the exceptions are not handled properly. HardFaults are at higher priority than any other exceptions with configurable priority. (Therefore HardFaults are not configurable!!!)
  
• MemManage: (User-Configurable Priority) MPU(Memory Protection Unit) determines his fault for both instruction and data transactions.

• BusFault: Memory related faults for instruction/data memory.
• UsageFault: Faults related to instruction execution.(Priority : 6 - 10) Including: 

           - an undefined instruction 

         - an illegal unaligned access

           - invalid state on instruction execution
           - an error on exception return 

• SVCall: (Priority 11-13) Triggered by the SVC(Supervisor Calls) instructions. Usually used to request privilege operations or to access OS kernel functions and device drivers.

• PendSV: (l4) Used for context switching.

• SysTick: (15) A decrement counter, which generates an exception on reaching zero.
• Interrupt(IRQ): (16) Generated by GPIO, UART, I2C, SSI, ADC, Timers, etc.

      4.  Exception Handlers:

• InterruptServiceRoutines(ISRs): Handles IRQ interrupts.
• Fault Handlers: HardFault, MemManage, BusFault, UsageFault.
• System Handlers: NMI, SVCall, PendSV, SysTick, 

       5.  Exception Priorities:

          #All programmable priorities has the default value of 0. 

       #NVIC supports group priority mechanism. That is, interrupt priority register will consist of two fields group priority and the sub-priority within the group. 

          #Comparison order for deciding execution order:

• Interrupts with higher Group priority can preempt the current handler
• Same group priority => compare sub-priority 
• Same sub-priority => Interrupt with the lowest IRQ number is processed first

       6.  Frequently-used Registers:

• InterruptSystem Handler Priority n (SYSPRIn):
• Interrupt Set Enable n (ENn):
• Interrupt Priority n (PRIn):

      7.  Vector Table: 

      

      8.  Common APIs:

• void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler) (void)):

Specifies where the code goes when interrupt happens.

• void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, uint32_t ui32IntType):

#ui32IntType=

{GPIO_FALLING_EDGE , GPIO_RISING_EDGE
GPIO_BOTH_EDGES , GPIO_LOW_LEVEL
GPIO_HIGH_LEVEL , GPIO_DISCRETE_INT}

• GPIOIntClear(GPIO_PORTF_BASE, GPIO_INT_PIN_4): 

This will clear the flag that tells the NVIC (a peripheral that takes care of interrupts) to go to the handler. If you don't clear it, it will create a infinite loop of always getting right back into the handler after leaving it.

It clears the interrupts for the specified pin, so that the another interrupt on the same pin can be detected again.( Usually, it takes few clock cycles to clear the interrupt after calling the function. Hence, it is recommended to call this function early in the interrupt handler. 

#ui32Port = The Base Address of the GPIO port.

#ui32IntFlags = GPIO_INT_PIN_0 | GPIO_INT_PIN_1…| GPIO_INT_DMA

• void GPIOIntEnable( uint32_t ui32Port, uint32_t ui32IntFlags): 

Enables the specified GPIO interrupts.

#ui32IntFlags : The same as above.

• void IntEnable(ui32Interrupt):

It enables the interrupt from the source.

       9.  Exception Entry and Return

• Preemption:When one exception preempts another, the exceptions are called nested exceptions. 
• Return: When the exception handler is completed, and there is no pending exception with sufficient priority(see PRIMASK, FAULTMASK and BASEPRI) to be serviced. The processor pops the stack and restores the processor state to the state before the interrupt occurred.
• Tail-Chaining: On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped( i.e. will will not return to stack) and control transfers to the new exception handler.
• Late-Arriving: A late-arriving interrupt is an interrupt which is recognized after the processor has started its exception entry procedure. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority and the vector fetch will be re-started using the vector for the late-arriving interrupt.

When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred to as stack frame(see Figure 2-7). 

      10.  Exception Return

     11.  More Facts:

#In the TM4C123 lauchpad each GPIO can only have 1 interrupt handler, meaning that you can't get separate handlers per pin.

# GPIO interrupts has 1. Edge-triggered 2. Level-sensing:(If an interrupt is set to level sensing  low, then it keeps calling the interrupt handler while the pin is 0)

Read P.101 2.5 Exception Model  for more info.

1. Fault Handling

• Fault Types:
• Fault Escalation and Hard Faults:
• Fault Status Registers and Fault Address Registers:
• Lockup: